1. Field of the Invention
The present invention relates to a time sequentially scanned display, for instance of liquid crystal type. Such displays may, for example, be used for time sequential colour displays, three-dimensional workstations, scientific visualisation, video games, videophones and three-dimensional television.
2. Description of the Related Art
In a known type of colour sequential display, the red, green and blue fields making up a complete colour frame are displayed one after the other sufficiently rapidly for an observer to perceive a colour image without substantial visible flicker. It is common for the image data to be supplied as a serial video signal with the individual colour data being supplied simultaneously in parallel. In order for this to be converted to the time sequential format for display, field or frame stores for storing complete fields or frames of image data must be provided.
Such stores may be provided externally of the display device itself. However, U.S. Pat. No. 5,225,823 discloses an arrangement in which such storage is integrated with the display device. Each picture element (pixel) of the display contains two stores (known as xe2x80x9cping-pongxe2x80x9d memories) for pixel image data. While one of these stores is being used to control the visual state of the pixel, pixel image data for the next frame may be written into the other store. However, the individual red, green and blue fields are not independently addressable and such an arrangement is only capable of a single first type of operation.
The xe2x80x9cfirst type of operationxe2x80x9d of a display is one in which there is a one-to-one correspondence between data addressing phases and data display phases. Thus, every data value addressed to a pixel is displayed once and only once. An example of this is disclosed in British Patent Application No. 9825152.3.
According to a first aspect of the invention, there is provided a time sequentially scanned display comprising a matrix of picture elements, each of which comprises a display element, an addressable latch having a plurality of storage locations and a first address input for selecting any one of the storage locations for storing image data, and a multiplexer for supplying image data from any one of the storage locations at a time to the display element, the multiplexer having a second address input for selecting which of the storage locations supplies image data to the display element.
Each of the picture elements may comprise an addressing arrangement for supplying addresses to the first and second address inputs.
Each of the addressing arrangements may comprise a counter whose output is connected to the first and second addressing inputs so that the storage locations are selected for storing image data in a first predetermined sequence and for supplying image data to the display element in a second predetermined sequence which is identical to but one step out of phase with the first predetermined sequence. The counter may have a clock input connected to the output of a transfer signal detector whose input is connected to a scan or data electrode of the matrix. The counter may be a modulo counter having a modulo control input provided with a latching arrangement.
Each of the addressing arrangements may comprise first and second counters whose outputs are connected to the first and second address inputs, respectively. The first counter may have a clock input connected to a scan electrode of the matrix. The second counter may have a clock input connected to the output of a transfer signal detector whose input is connected to a or the scan electrode or a data electrode of the matrix.
The addressing arrangement may comprise a reset arrangement for resetting the first and second counters when power is applied to the display.
The first and second counters may be modulo counters having modulo control inputs provided with a latching arrangement.
The latching arrangement may have data inputs connected to at least some outputs of the storage locations. The latching arrangement may be arranged to be enabled by an output of a decoder. The decoder may comprise a counter having a clock input connected to the output of the transfer signal detector and a reset input connected to a or the scan electrode.
Each addressable latch may comprise an analog addressable latch.
Each addressable latch may comprise a latch having the plurality of storage locations and a demultiplexer for selectively supplying the image data to any one of the storage locations.
Each addressable latch may have a clock input connected to a or the scan electrode and a data input connected to a or the data electrode.
Each addressable latch may have storage locations for red, green and blue image data.
Each addressable latch may have storage locations for red, green, blue and intensity image data.
Each addressable latch may have storage locations for red, green and blue image data for two image fields or frames.
Each addressable latch may have storage locations for red, green, blue, white and/or black image data. The storage locations for the white and/or black image data may be hard-wired to receive voltage levels which are not addressable.
The display may comprise a multi-colour backlight and a backlight controller.
Each display element may comprise a liquid crystal picture element. Each display element may be of reflective type. The addressable latches and the multiplexers may be embodied as crystalline silicon or poly-silicon. The addressable latches and the multiplexers may be disposed behind the reflective display elements.
According to a second aspect of the invention, there is provided a method of operating a display according to the first aspect of the invention, comprising supplying image data to the picture elements in first sets of time-sequential addressing phases with each first set constituting a frame of image data and displaying the image data in second sets of time-sequential display phases with each second set constituting a frame of image data, the number of display phases in each of the second sets being greater than the number of addressing phases in each of the first sets. The addressing phases of each of the first sets may comprise different component colour addressing phases, the display phases of each of the second sets may comprise component colour display phases, and at least one of the component colour display phases may be repeated in each of the second sets. A green phase may be repeated in each of the second sets.
The number of display phases in each of the second sets may be an integer multiple of the number of addressing phases in each of the first sets. All of the colour component display phases may be repeated the same number of times in each of the second sets.
White and/or black addressing phases may occur in only some of the first sets.
The maximum electro-optic response time of the liquid crystal picture elements may be substantially equal to or less than the duration of each of the display phases.
The image data supplied during at least some of the addressing phases may comprise or contain control data for controlling an aspect of pixel operation. The aspect of pixel operation may comprise the modulo of each modulo counter.
It is thus possible to provide a display which can be operated in other than the first type of operation referred to hereinbefore. In particular, such a display is capable of a second type of operation (as well as being capable of the first type of operation). According to the second type of operation, the number of data display phases is an integral number greater than the number of data addressing phases. Thus, an addressed or stored value may be displayed during more than one time slot, between which different data may be displayed. In other words, the data addressing phase and the data display phase of the display need not be in a one-to-one relationship, as is necessary in known types of time sequentially scanned displays. For example, data addressing may be performed at a refresh rate of 30 Hz whereas the data display refreshing may be performed at 60 Hz so as to reduce the visibility of image flicker as compared with the first type operation. In fact, the addressing rate of the display may be substantially reduced without compromising the display flicker performance. This may reduce radio frequency emissions generated by the display. Also, a reduced input data rate allows the design of display scanning electronics to be simplified, particularly for integrated poly-silicon drivers.
Lower addressing rates may result in reduced power consumption. The second type of operation may permit reduced power reversionary modes of operation. For example, it is possible to operate such a display in an intensity (Y) only reversionary power saving mode, which may be useful in portable products to prolong operation when battery charge is low. Also, different parts of a display may operate in different modes offering further opportunities for saving power during normal operation.
A display of this type is capable of operating in different modes depending on the requirements of the specific application. Further, individual parts such as lines, groups of lines, pixels or groups of pixels, may operate in different modes so as to provide a very versatile display. Examples of such modes include repeating one or more of the fields in any display cycle, for instance to provide RGGB or RGBG display from RGB data. The display addressing cycles may load different data in sub-views, such as RG1BG2 so that the G1 and G2 fields (which may contain different data) are integrated by the eye to obtain a greyscale value. A field may not be addressed but nethertheless may be displayed, for example to implement a black (K) blanking phase. Each frame may include a luminence or intensity (Y) phase to maximise brightness.
As described hereinafter, at least one line of a display may be configured by an instruction word which has previously been down-loaded to the pixels. Down-loading of digital instruction words may share the same path as, for example, ordinary analog data signals to the pixels.
The display may display xe2x80x9cconstantsxe2x80x9d such as xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d which are stored at the pixels. Although such values may be down-loaded in the same way as other image data, it is also possible for this to be achieved by xe2x80x9chard-wiringxe2x80x9d at the pixels.
Some embodiments of the invention are also capable of a third type of operation. According to the third type of operation, the number and order of data display phases are fully independent of the number and order of data addressing phases.